1. Field of the Invention
The present invention relates to programmable gate arrays which include an array of configurable logic cells, a plurality of input/output cells, and a configurable interconnect structure. More particularly, the present invention relates to programmable gate arrays with logic cells having individually configurable output enable circuits.
2. Description of Related Art
The programmable gate array is a high performance, user programmable device containing three types of configurable elements that are customized to a user's system design. The three elements are (1) an array of configurable logic blocks (CLBs), (2) with input/output blocks (IOBs) around a perimeter, all linked by (3) a flexible programmable interconnect structure.
The system design desired by a user is implemented in the device by configuring programmable RAM cells. These RAM cells control the logic functionality performed by the CLBs, IOBs and the interconnect. The configuration is implemented using PGA design software tools.
It is generally accepted that the programmable gate array was first, successfully, commercially introduced by Xilinx of San Jose, Calif. Xilinx originally introduced the XC2000 series of logic cell arrays and has more recently introduced a second generation XC3000 family of integrated circuit programmable gate arrays. A description of the 2000 series, as well as related programmable logic device art, can be found in THE PROGRAMMABLE GATE ARRAY DESIGN HANDBOOK, First Edition, published by Xilinx, pages 1-1 through 1-31. The architecture for the XC3000 family is provided in a technical data handbook published by Xilinx entitled XC3000 LOGIC CELL ARRAY FAMILY, pages 1-31. (See, in particular, FIG. 15b re three-state buffers in the interconnect structure.) Each of these Xilinx publications is incorporated by reference in this application as providing a description of the prior art.
The prior art in programmable gate arrays is further exemplified by U.S. Pat. Nos. 4,642,487; 4,706,216; 4,713,557; and 4,758,985; each of which is assigned to Xilinx, Inc. These U.S. Patents are incorporated by reference as setting forth detailed descriptions of the programmable gate array architecture and implementations of the same.
As mentioned above, the programmable gate array consists of a configurable interconnect, a ring of configurable input/output blocks, and an array of configurable logic blocks. It is the combination of these three major features that provides flexibility and data processing power for programmable gate arrays. However, the programmable gate arrays of the prior art suffer certain limitations in each of the interconnect structure, the input/output block structures, and the configurable logic block structures.
One of the limitations resides in the flexibility of the connections from outputs of the configurable logic cells to the interconnect structure. For instance, it is often desirable to have a tristatable output with an output enable logic, in certain parts of a network. Prior art systems have distributed tristate buffers in the interconnect structure to serve this purpose. However, utilization of the interconnect structure to reach the tristate buffers, and the limited number of tristate buffers, have increased the complexity of programming the programmable gate arrays implemented in this manner.
Accordingly, it is desirable to implement the logic cells in the programmable gate array with flexible, programmable output structures for connection to the configurable interconnect.